Generic and low-cost digital signal processing chips for coherent optical transceivers are required for the 100G metro market, argues Dr Maxim Kuschnerov
Digital signal processing (DSP) integrated circuits were an enabler of the transition from 10G and 40G interfaces to 100G in optical networks. These chips are instrumental in unravelling the information that is received using coherent detection, while compensating for several types of fibre impairments that would otherwise render the signal unintelligible.
In the first phase of 100G deployments, which started in 2010, ownership of DSP development was critical because it allowed vendors to gain a time-to-market advantage. As a result most of the larger optical network equipment manufacturers implemented internal DSP programs, while the merchant silicon vendors had to fight for the much smaller secondary market or opportunistic design-ins.
As technology matures, a shake-out of internal DSP programs and emergence of off-the-shelf products is a natural process that is to be expected – indeed, analysts predicted that this could happen as early as 2014. However, to date nothing substantial has changed in the market, raising uncomfortable questions about what needs to happen for merchant silicon suppliers to take over the 100G market.
The rise of metro 100G
Deployment of 100G wavelengths is picking up steam in metro and regional networks, with the market being dominated by coherent technology as opposed to direct detect optics. According to a recent survey by market research firm IIR, metro 100G as a percentage of newly-installed speeds jumped from only 6 per cent last year to 21 per cent currently.
This adoption has happened in spite of the fact that 10G is far from losing its importance in metro, as the market pricing for coherent 100G is still greater than 10G on a cost-per-bit basis, including the so-called ‘muxponder tax’ of unfilled 100G lambdas. Moreover, the majority of metro networks are fibre rich, and the higher spectral efficiency of coherent technology is not as easily leveraged in this network domain.
Metro demand is important because it drives up volumes, in turn driving down costs – which are currently still high. A rough estimate puts the costs to develop a 100G metro DSP in the region of $25 – 30 million.
This includes the engineering resources for the design and verification of the digital core logic including the modem, forward error correction (FEC) and external intellectual property (IP) blocks, software and API development, physical design and backend, mask and fab lot costs, as well the evaluation and testing of the devices. Companies missing critical IP blocks like digital-to-analogue and analogue-to-digital converters, SerDes or OTN framing, must pay royalties to third parties.
The material costs of a DSP also include the actual silicon and packaging, as well as operational costs such as assembly and testing. Good control of the value chain in chip design is crucial in order to produce a mass-market DSP with the lowest production costs right out of the gate.
Volume will determine the final pricing of 100G DSP chips. This is not say that one can achieve something like $27.50 like the latest wireless processor in Apple’s iPhone 6s – possible thanks to much higher volumes and less sophisticated packaging in wireless communication devices. Still, with the 100G market expected to peak at around one million interfaces shipped in 2020, a generic 100G DSP has the potential to bottom out at a market pricing of roughly 10x more than its wireless counterpart, assuming it reaches sufficient scale.
What are the conditions to achieve a high scalability in the market for a single DSP device while simultaneously avoiding the dangers of too many parallel developments by system houses and merchant silicon suppliers? This is a key question, as the industry wants to avoid repeating the mistakes of the past.
Not surprisingly, the DSPs should cover the basic requirements for metro and regional networks, such as a 100G and 200G line rates, without fancy bells and whistles. Taking differentiation out of these devices is imperative. The industry has seen a push by the likes of Deutsche Telekom to standardise a so-called ‘Black Link’ that enables optical interworking between several chip suppliers using a standard error correction scheme. While this standard leads to a lower overall reach, it is sufficient to cover the sweet spots in metro networks.
Once this generic chip behaviour has been achieved, greater emphasis can be put on differentiation in the higher layers of communication networks, through technologies such as software defined networking (SDN). This evolution would support the overall industry trend that complexity migrates from hardware to software, with network management and operational aspects such as ease of commissioning and automation becoming more important in the future.
For a generic 100G ‘white box’ DSP, the only remaining features of interest will be power and cost. Such parts are expected to arrive on the market in 2016 – and could be a turning point for the industry that will see a final shake-out of in-house 100G DSP programmes at the network equipment manufacturers.
So far so good, but how will the industry react to the arrival of 400Gb/s and Terabit Ethernet? DSPs will certainly remain an integral part of future coherent interfaces, however the relative importance could be diminished. Back in the day Nortel revolutionized optical transmission by its aggressive move into 40Gb/s coherent DSP technology, going first where no one else dared to go and breaking down barriers for everyone else to follow. However, after 10 years of coherent DSP development, this feature growth seems to be flattening out, with the industry on the hunt for the next big technological advance. Whether it’s integrated monolithic low cost optics, optical layer disaggregation, or transport SDN – optical business doesn’t seem to lack potential directions for years to come.
- Dr. Maxim Kuschnerov is a principal product manager for DWDM technology at Coriant, Munich, responsible for high-speed interfaces and photonic layer technology