Complementary metal-oxidesemiconductor (CMOS) technology has come a long way since its invention in 1963 by Frank Wanlass during his time employed at Fairchild semiconductor.
In fact, according to Paul Momtahan, director of solutions at Infinera, we are seeing a major improvement in the process node every couple of years. He explained: ‘From 28 to 16 to 7nm and the next one is 5nm. Every time you do that with the same area of silicon, you get better performance, reduce power consumption and things can be made smaller.’
With this in mind, the next consideration, for developing optical engines, is how this kind of improvement in technology can be leveraged for coherent digital signal processors (DSPs).
Power play ‘You have three options to take advantage of that,’ said Momtahan. ‘One is to build the most powerful DSP you can with the highest baud rates and all these advanced features that require lots of processing, like Nyquist, subcarriers, and probabilistic constellation shaping... all that exciting technology, and you’re really improving on the performance vector.’ The main benefits include more wavelength capacity for a given reach, and better spectral efficiency.
A second way to take advantage of developments in silicon, said Momtahan, is to scale down the size of the DSP. ‘Rather than building a big bit of silicon, as you would with, say ICE6 [Infinera’s sixth-generation optical engine], you can build a small DSP, and really get the power consumption down. So when you think about a 400ZR, what you’re really doing is optimising for that power and space vector.’
This, he said, would enable a reduction in power consumption, brought about in a pluggable form factor. ‘You can then put that directly into a router or into an expander,’ he continued, ‘to gain the benefits of playability.’
A third way to harness silicon development potential, said Momtahan, is to integrate systems-level functions to the applicationspecific integrated circuit (ASIC).
‘In the past,’ he explained, ‘you would have had multiple chips. A separate chip for framing and forward error correction, and at one point, you would even have had separate components for the digital analogue converter and the analogue-to-digital converter.
‘What the industry has done over time is integrate several of those functions into the ASIC, so we will normally refer to the DSP, but the DSP is actually only one function on that chip. You get a lot of other functions – encryption is now commonly there, for example,' Momtahan continued.
‘As we get more processing power, you can use some of that additional processing power to integrate more systems-level functions onto the optical engine. So, you can put some manageability, then turn that pluggable, for example, into an exponder.’
This allows numerous functions to be included in the ASIC, including demarcation, the spectrum analyser etc… all enabled by the aforementioned improvements in the CMOS process node.
Momtahan said: ‘You’ve got embedded, and you’ve got pluggables, and essentially the industry is making different priorities, in terms of these three vectors. Embedded optical engines like ICE6 and Ciena’s WaveLogic 5 Extreme are really prioritising this performance dimension.’
This low space and power dimension are being prioritised, particularly for 400ZR and 100ZR developments, explained Momtahan. In addition, as the CMOS process is improved, it starts to open up opportunities to bring some of these advanced functions previously only possible in embedded, into the pluggable optical engine.
‘Things like Nyquist, subcarriers and probabilistic constellation shaping,’ explained Momtahan, ‘they start to become possible implantables, and that’s because you’ve got this extra processing power.’
Similarly, some of the systems-level functions can be brought into the pluggable. This is a key focus for Infinera, with its XR optics pointto-multipoint coherent optical sub-carrier aggregation technology. ‘This means that the pluggable becomes like an open xponder,’ said Momtahan.
So, to address the wide-ranging set of transceiver selection criteria, embedded 800G and the various flavours of pluggable (100ZR,400ZR, XR optics, Open ROADM, OpenZR+). Momtahan believes these three vectors can be prioritised differently, allowing each to have its own sweet spots that work for an individual application.
While better silicon technology enables the evolution of coherent technology along these three vectors, there are also additional tradeoffs related to, for example, performance versus form factor, or performance versus multi-vendor interoperability.
Momtahan explained: ‘When you build QSFP-DD, you are quite constrained in terms of space. So the transmit power is normally quite challenged. Whereas in something like a CFP 2 or an embedded optical engine, you can put some extra amplifiers in there, because you’ve got a bit more space.’
He feels another trade-off is band noise. ‘When you have a transceiver and it transmits the wavelength, you can also get noise that is not within the spectrum of the wavelength. This either comes from amplifications, or it can be a byproduct of the laser. It’s called out-of-band noise. What you can do in a larger form factor is put a tuneable optical filter in there to block it. Whereas in a QSFP-DD, you can’t put that there... so all of that noise can add together. That can create some challenges. So there are some other trade-offs outside of the main three vectors that you have related to the physical size of the form factor, whether you can put in these extra functions or not.’
Going forward, Momtahan believes that embedded and pluggables will co-exist in the market for some time to come. ‘There’s no one size fits all,’ he concluded. ‘The market is going to have pluggables and it will also have embedded, because these three vectors are prioritised differently to more optimally address different applications. There will be a market for embedded and a market for pluggable, at least for the next couple of generations.’
This white paper explores how silicon technology enhancements are enabling the evolution of coherent optical engines along three vectors.
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