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TeraSquare, of Korea, a leading company in fabless semiconductor development, has unveiled a parallel CDR (clock data recovery) solution that is says dramatically improves signal quality across 100G systems and make massive power consumption savings in the process.
TeraSquare’s parallel CDR- TS-CM44013 slashes Integrated Chip (IC) power consumption to 0.75w compared to average CFP4 levels of 3.5w, does not require a clock reference and has built in JTOL testability- avoiding the current expensive requirement for external testing equipment.
'Our new IC is truly revolutionary and we are very excited about being able to demonstrate it at ECOC- where we will be exhibiting for the very first time,' said TeraSquare CTO, Jinho Park. 'It is, by a considerable margin, the lowest power solution the market has ever seen and this critical requirement is just one of the major features that we believe will make our new development so significant across the world.'


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