A tale of two startups

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Mark Lutkowitz makes a comparison between solutions from two startups, demonstrated at ECOC 2021

Being in person at ECOC 2021, I had the opportunity to take a close look at the new solution from startup, Avicena, which interconnects chips using microLEDs. Indeed, there are some fascinating, technical aspects to the product that may turn out to be over-ambitious but appear to result in attractive attributes of high density and low power. 

There are also expected to be some tough challenges for Avicena in effectively competing against present offerings in the space, as well as dealing with hurdles totally outside of its control, as the supplier focuses on the rather limited goal of optimising interfaces which only represents a single, low-end piece of fully disaggregated systems.

At the same time, the optical interface by itself is often underappreciated. Avicena claims it can fully take advantage of previous investments in the uLED display space, with 10Gb/s lanes resulting in terabit capability.

If one assumes that Avicena can fully execute on the promise of LightBundle, such as with production viability, at least one large hyperscaler is apparently bullish on its prospects, including from a cost perspective. The vendor’s parallel optical links are for either rack level disaggregation interconnect or for die-to-die connection that can span a total of 10m. 

Opportunity knocks

Besides the webscalers, Avicena anticipates opportunities with the IC, automotive, and image sensor companies. Although Avicena is certainly not the first company to pitch massively parallel LED links for C2C, it does have many new ideas on the approach – and the metrics of the device make sense as well.

However, skeptics are concerned that GaN-based emitters may not be ready to do the job. Conversely, they agree that blue light will help in integrating the PDs directly on the silicon. Cynics may also assert that the difficulty with 2D arrays of LEDs is the breakout of individual devices. The argument is based on getting a 10G diff pair to each LED, without crosstalk or SI problems.

Avicena’s response to that statement is that it does modulate each device, simultaneously translating the wide electrical bus into a wide optical bus. The firm points out that the LEDs are driven by relatively low currents. 

The supplier goes on to say that while there is always crosstalk, especially in the receivers, and at a few Gb/s, it is easy to manage. Mostly, there needs to be an awareness of ground bounce along with having good decoupling capacitors.

Keeping it simple

An enabler of the benefits for Avicena is that it has the attractive aspect of using simple, mature, NRZ modulation. Undoubtedly, low, slow, and massively parallel is better for many apps like computer-to-computer than SerDes-based interfaces with their necessity for clocking and synchronisation.

Yet, Avicena’s ability to displace current cabling will come head-on with the inventory obstacles of carrying multiple types that exist today in large data centres, encompassing single mode fibre, multimode fibre, as well as copper. For example, active electrical cables that go beyond the 2m passive range have not seemed to catch on at all in such facilities, as active optical cables are the obvious preference. 

In looking at the future of data centre servers to leaf-spine interconnect, and the desire for 20m length to support rack-to-rack links, the AOCs are preferable. Whereas Avicena will contend that it is only looking to displace copper, for now, at least, the ostensible limitation of the LightBundle is that it can evidently only reach half of that preferred distance.

Moreover, future adaptations to copper infrastructure, which would permit it to remain viable against Avicena, at 2m and under, can never be ruled out. Besides, there is the supplemental, practical concern as to the extent to which low-speed, optical links will attract the attention of host-card designers.

Minimisation

Additionally, while VCSELs are not going away, the high cost associated with multimode fibre at higher speeds in new data centres is making the use of such strands increasingly problematic. Avicena is planning on introducing not only specialised, plastic multimode fibre, but strung together in a multicore structure to minimise size, which has otherwise not been expected to find acceptance for communications purposes in general for as long as several years.

The good news for Avicena is that a player that seems to be similar in scope in terms of an application level, Ayar Labs, is not a direct competitive threat, despite the latter being far ahead of the former in both product development and providing actual, detailed data publicly on the device’s performance. To be sure, Avicena is attacking very short-reach copper (and arguably multimode fibre targets), and relating to the former, touting greater than a 100 times improvement, while Ayar is pushing at considerably longer single mode fibre data centre interconnect. 

Most importantly, whether the discussion is about Avicena or Ayar, or other types of specialists, such as Fungible and Pensando, they are all part of a highly complex matter. There can be no doubt that disaggregation itself is a logical process in the appropriate sector because technologies mature and innovate at different timeframes.

So, enabling upgrades of separate functions is valuable for large-scale data centres. Still, it seems that a Fungible is just touching the optimisation of the network, but not necessarily addressing the full disaggregation need (for instance, there is quite little memory disaggregation support). 

The management aspect of this is tied to the whole operational aspect of the data centres. For mid-size and smaller enterprises, the administrative overhead might be too much for the given value.

Need for speed

It should be further noted that in a public presentation, Arista Networks’ chairman, Andy Bechtolsheim, stated that he discovered that his investments in lots of startups that were associated with fancy, fast storage, GPU, and caching techniques had diminishing returns if only optimising a single segment. He discovered that the overall network speed increase had made such developments moot.

The remaining problem with disaggregation, including what is being proposed by Avicena, is that regardless of the rate of the interface, the speed of light obviously cannot be altered nor the distance latency. Moreover, it is preferable for the cache latency to stay at one clock cycle. 

It will be interesting to see how a new bus protocol, CXL 3.0, will get each of the pieces together. Then seeing how CXL evolves will also be intriguing. 

Actually, there are some networking engineers, who will even insist that the physical challenges, latency, etc. are likely bigger than how to manage everything. They maintain that the computer industry and data centre operators have long figured out how to manage distributed systems through many years of practice (not just in research). 

The realisation and assurance of the performance is the critical aspect, according to this school of thought. While the case can be made that Moore’s Law went extinct some years ago, the requirements for computing keep growing. 

Therefore, it becomes about protocols and PCIe switches. Recently, they both have attracted lots of attention. 

Furthermore, while manufacturers like selling the concept of just buying different chips and putting them together, they do not necessarily understand how that will work in practice. In fairness to Avicena, it is planning to have board-mounted chips with PCIe/CXL.

Mark Lutkowitz is principal at fibeReality, LLC

Image credit: Joerg Lantelme/Shutterstock.com

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Image credit: Joerg Lantelme/Shutterstock.com

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